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| DIGITAL SIGNAL PROCESSOR S5L9291X INTRODUCTION 100-TQFP-1414 S5L9291X is a signal processing LSI for the CD. Digital processing functions (EFM demodulation, error correction), spindle motor servo processing, compression for anti-rolling and anti-shock, expandable memory control functions (4M, 16M, 64M EDO/Fast Page DRAM and 16M, 32M, 64M, 128M, 256M SDRAM ), 10-band EQ (Equalizer) Filter, CD-Text and 1-bit DAC for the CD-MP3 Interface are installed in S5L9291X. FEATURES * Signal processing part EFM data demodulation Frame sync detection, protection, insertion Sub code data processing (Q data CRC check, Q data register installed) Error correction (C1: 2 error correction, C2: 4 erasure correction) Installed 16K SRAM for De-interleave Interpolation Digital audio interface CLV/pseudo-CAV servo control Wide capture range digital PLL ( 50%) CD-Text Variable speed CLV Control (x1 to x2 ) CD MP3 Interface * Digital filter, DAC part 4 times over sampling digital filter Digital de-emphasis 10 Band EQ function Sigma-delta stereo DAC installed Audio L.P.F installed * Memory control part 4/5/6 bit compression and expandable control Full bit control 4M/16M/64M, x4, x8, x16 EDO/FastPage DRAM Support 16M/64M/128M/256M, 32M(16M 2EA), x8, x16 SDRAM Support ORDERING INFORMATION Device S5L9291X01-T0R0 Package 100-TQFP-1414 Supply Voltage 2.7 to 3.3V Operating Temperature -20 to +75C 1 S5L9291X DIGITAL SIGNAL PROCESSOR BLOCK DIAGRAM SOS1 SQCK SQDT SBCK SBDT C2PO DATX VCO1LP VCO2LP EFMI LOCK SMEF SMON SMDP SMDS WDCK TESTV WFCK RFCK C4M XIN ISTAT MLT MDAT MCK MUTE DPLL Subcode Out Digital Out EFM Demodulator Interpolator Digital Filter CLV Servo ECC I/O Interface 1-bit DAC Timing Generator 16K SRAM Encoder Decoder PWM Micom Interface Address Generator DRAM Interface LPF JITB AD9 - AD0 D3 - D0 CAS1 - CAS0 RAS WE LCHOUT RCHOUT VHALF VREF 2 DIGITAL SIGNAL PROCESSOR S5L9291X PIN CONFIGURATION VDDD6 VDDD5 VSSD5 VSSD4 BA1 (CS1) AD10 CAS RAS CS0 AD0 AD1 AD2 AD3 AD4 77 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 VDDA_PLL VSSA_PLL VCO1LF VCO2LF VSSD_PLL VDDD_PLL PBCK VDDD1 XIN XOUT VSSD1 TEST0 EFMI LOCK SMEF SMON SMDP SMDS WDCK VDDD2 TESTV WFCK LKFS RESETB MLT 76 AD5 BA0 WE D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 AD6 AD7 AD8 AD9 AD11 AD12 CLK D8 D9 D10 D11 D12 D13 D14 D15 VDDD4 VSSD3 MNT5 MNT4 MNT3 MNT2 MNT1 MNT0 RFCK C2PO S5L9291X (CDDSP+ESP) 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 DATX VSSA_DAC VSSD2 S0S1 VHALF ISTAT SQCK MDAT MUTE SQDT TEST1 TEST2 VDDD_DAC VDDA_DAC RCHOUT VDDD3 VSSD_DAC LCHOUT TEST3 SBCK SBDT VREF MCK C4M JITB 50 3 S5L9291X DIGITAL SIGNAL PROCESSOR PIN DESCRIPTION Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol VDDA_PLL VSSA_PLL VCO1LF VCO2LF VSSD_PLL VDDD_PLL PBCK VDDD1 XIN XOUT VSSD1 TEST0 EFMI LOCK SMEF SMON SMDP SMDS WDCK VDDD2 TESTV WFCK LKFS RESETB MLT MDAT MCK ISTAT S0S1 SQCK SQDT VDDD3 VSSD2 I/O O O O I O I I O O O O O O I O O I I I I O I/O I O Analog power for DPLL Analog ground for DPLL Pump out for VCO1 Pump out for VCO2 Digital ground separated bulk bias for DPLL Digital power separated bulk bias for DPLL VCO1/2 clock output (4.3218MHz) Digital power X'tal oscillator input (16.9344MHz) X'tal oscillator output Digital ground Test input EFM signal input CLV servo locking status output LPF time constant control of the spindle servo error signal ON/off control signal for spindle servo Phase control output for spindle motor drive Speed control output for spindle motor drive Word clock output (x1: 88.2kHz, x2: 176.4kHz) Digital power Various test input Write base clock output The lock status output of frame sync System reset at "L" Latch signal input from micom Serial data input from micom Serial data receiving clock input from micom The internal status output to micom (3-state output) Subcode sync signal (S0+S1) output Subcode-Q data transferring bit clock input Subcode-Q data serial output Digital Power Digital Ground Description 4 DIGITAL SIGNAL PROCESSOR S5L9291X PIN DESCRIPTION (Continued) Pin No 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Symbol SBCK SBDT MUTE C4M TEST1 TEST2 LCHOUT VDDA_DAC VHALF VREF VSSA_DAC RCHOUT VDDD_DAC VSSD_DAC TEST3 DATX JITB C2PO RFCK MNT0 MNT1 MNT2 MNT3 MNT4 MNT5 VSSD3 VDDD4 D15 D14 D13 D12 D11 D10 D9 I/O I I/O I O I I O O O O I O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Subcode data transferring bit clock Subcode data serial output System mute at "H" 4.2336MHz clock output Test Input Test Input Left-Channel audio output through DAC Analog Power for DAC Reference Voltage output for bypass Reference Voltage output for bypass Analog Ground for DAC Right-Channel audio output through DAC Digital Power for DAC Digital Ground for DAC Test Input Digital audio data output Internal SRAM jitter margin status output C2 pointer Output Read base clock output Monitoring signal output Monitoring signal output Monitoring signal output Monitoring signal output Monitoring signal output Monitoring signal output Digital Ground Digital Power DRAM data Input/Output 15 (3-State Output) DRAM data input/output 14 (3-State Output) DRAM data input/output 13 (3-State Output) DRAM data input/output 12 (3-State Output) DRAM data input/output 11 (3-State Output) DRAM data input/output 10 (3-State Output) DRAM data input/output 9 (3-State Output) Description 5 S5L9291X DIGITAL SIGNAL PROCESSOR PIN DESCRIPTION (Continued) Pin No 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol D8 CLK AD12 AD11 AD9 AD8 AD7 AD6 AD5 AD4 AD3 VSSD4 VDDD5 AD2 AD1 AD0 AD10 BA1(CS1) BA0 CS0 RAS CAS WE VSSD5 VDDD6 D7 D6 D5 D4 D3 D2 D1 D0 I/O I/O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O Description DRAM data input/output 8 (3-State Output) SDRAM Clock(4MHz) (3-State Output DRAM address output 12 (3-state output) DRAM address output 11 (3-state output) DRAM address output 9 (3-state output) DRAM address output 8 (3-state output) DRAM address output 7 (3-state output) DRAM address output 6 (3-state output) DRAM address output 5 (3-state output) DRAM address output 4 (3-state output) DRAM address output 3 (3-state output) Digital Ground Digital Power DRAM address output 2 (3-state output) DRAM address output 1 (3-state output) DRAM address output 0 (3-state output) DRAM address output 10 (3-state output) Bank Address 1 / DRAM Chip Select 1 (3-State Output) Bank Address 0 (3-State Output) DRAM Chip Select 0 (3-State Output) DRAM Row Address Selection output (active Low) (3-State Output) DRAM Column Address Selection output 0 (active Low) (3-State Output) DRAM Write Enable output (active Low) (3-State Output) Digital Ground Digital Power DRAM data Input/Output 7 (3-State Output) DRAM data Input/Output 6 (3-State Output) DRAM data Input/Output 5 (3-State Output) DRAM data Input/Output 4 (3-State Output) DRAM data Input/Output 3 (3-State Output) DRAM data Input/Output 2 (3-State Output) DRAM data Input/Output 1 (3-State Output) DRAM data Input/Output 0 (3-State Output) 6 DIGITAL SIGNAL PROCESSOR S5L9291X MAXIMUM ABSOLUTE RATINGS Item Power supply voltage Input supply voltage Operating temperature Storage temperature Symbol VDD VI TOPR TSTG Rating -0.3 to 3.8 -0.3 to VDD + 0.3 -20 to 75 -40 to 125 Unit V V C C ELECTRICAL CHARACTERISTICS OPERATING CONDITION Item Power supply voltage Operating temp. Symbol VDD TOPR Operating Range 2.7 to 3.3 -20 to 75 Unit V C 7 S5L9291X DIGITAL SIGNAL PROCESSOR DC CHARACTERISTIC (VDD = 3.0V, VSS = 0V, Ta = 25C) Item 'H' input voltage1 'L' input voltage1 'H' output voltage1 'L' output voltage1 'H' output voltage2 'L' output voltage2 'H' output voltage3 'L' output voltage3 Input leak current1 Input leak current2 Three state output leak current Symbol VIH VIL VOH(1) VOL(1) VOH(2) VOL(2) VOH(3) VOL(3) ILKG1 ILKG2 IO(LKG) IOH = -1mA IOL = 1mA IOH = -1mA IOL = 1mA IOH = -1mA IOL = 1mA VI = 0-VDD VI = 0-VDD VO = 0-VDD Condition Min 0.8VDD 2.4 2.4 2.4 -10 -10 -10 Design Values Typ Max 0.2VDD 0.4 0.4 0.4 10 10 10 V V V V V V V V uA uA uA (Note 5) (Note 6) (Note 7) (Note 4) (Note 3) (Note 2) (Note 1) Unit Comment NOTES: 1. Related pins: All input, bi-direction terminal (input mode) 2. Related pins: All output terminal 3. Related pins: All bi-direction terminal (output mode) 4. Related pins: All tri-state output terminal 5. Related pins: All input terminal (excluding XIN ) 6. Related pins: XIN 7. Related pins: SMEF, SMDP, SMDS, ISTAT 8 DIGITAL SIGNAL PROCESSOR S5L9291X AC CHARACTERISTIC When Pulse is Applied to XIN (Ta = 25C, VDD = 3.0V, VSS = 0V) Item 'H' level pulse width 'L' level pulse width Pulse frequency Input 'H' level Input 'L' level Rising & falling time Symbol TWH TWL TCK VIH VIL TR,TF Min 13 13 26 VDD-1.0 Typ Max 0.8 10 Unit ns ns ns V V ns TCK TWH TWL VIH_max VIH_max*0.9 VDD/2 VIL_max*0.1 VIL_min TR TF 9 S5L9291X DIGITAL SIGNAL PROCESSOR MCK, MDAT, MLT, SQCK (Ta = 25C, VDD = 3.0V, VSS = 0V) Item Clock frequency Clock pule width Setup time Hold time Delay time Latch pulse width SQCK frequency SQCK pulse width Symbol FCK1 TWCK1 TSU TH TD TW FCK2 TWCK2 Max 1 1 Typ Min 500 300 300 300 1000 500 Unit MHz ns ns Ns Ns ns MHz ns 1/FCK1 TWCK1 MCK MDAT MLT SQCK TWCK2 TWCK2 1/FCK2 SQDT TSU TH TSU TH TD TW TWCK1 10 DIGITAL SIGNAL PROCESSOR S5L9291X EDO-DRAM, FAST-PAGE DRAM INTERFACE TIMING Read Cycle 1T = 59ns/2 at Bus X4 1T = 59ns at Bus X8, X16 2T Don't Care OE = GND 4T RAS 2T CAS 1T ADDR 1T 4T 2T ROW ADDRESS COLUMN ADDRESS WE 1T DATA[3:0] 1T DATA-OUT Write Cycle 4T RAS 2T CAS 1T ADDR 1T 4T 2T 1T = 59ns/2 at Bus X4 1T = 59ns at Bus X8, X16 2T Don't Care OE = GND ROW ADDRESS COLUMN ADDRESS WE 2T DATA[3:0] DATA-IN 2T 11 S5L9291X DIGITAL SIGNAL PROCESSOR CAS-BEFORE-RAS Refresh Cycle RAS 1T = 59ns/2 at Bus X4 1T = 59ns at Bus X8, X16 2T 2T CAS 12 DIGITAL SIGNAL PROCESSOR S5L9291X SDRAM INTERFACE TIMING READ (with auto precharge) Cycle CAS Latency 2 1T=59ns at Bus X8,X16 Don't Care CS = GND CKE = VDD DQM = GND CLK 4T RAS 2T CAS 4T ADDR A0-A9,A11 ROW ADDRESS COLUMN ADDRESS 2T 2T WE DATA[3:0] enable auto precharge A10 ROW ADDRESS DATA-OUT BA0,BA1 BANK BANK 13 S5L9291X DIGITAL SIGNAL PROCESSOR Write (with auto precharge) Cycle CAS Latency 2 1T=59ns at Bus X8,X16 Don't Care CS = GND CKE = VDD DQM = GND CLK 4T RAS 2T CAS COLUMN ADDRESS 2T 2T ADDR ROW ADDRESS WE DATA[3:0] DATA-OUT enable auto precharge A10 ROW ADDRESS BA0,BA1 BANK BANK Auto Refresh Cycle CAS Latency 2 1T=59ns at Bus X8,X16 Don't Care CS = GND WE = VDD CKE = VDD CLK 2T RAS 2T CAS 14 DIGITAL SIGNAL PROCESSOR S5L9291X DESCRIPTION OF OPERATION MICOM INTERFACE Each command is executed when data and command is input as LSB first according to timing shown in the figure below through MDAT, MCK, and MLT inputs and ISTAT output. * * * Read/Write mode support Address: 8-bit Data: 8-bit (writing), 8/16-bit (reading) (Write Cycle) MDAT MCK MLT Register valid D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 [MSB] (Read Cycle-1: $B5, $B6) MDAT MCK MLT ISTAT S7 S6 S5 S4 S3 S2 S1 S0 D8 D9 D10 D11 D12 D13 D14 D15 [MSB] ... (Read Cycle-2: $B7) MDAT MCK MLT ISTAT R15 R14 R13 R12-R3 R2 R1 R0 D8 D9 D10 D11 D12 D13 D14 D15 [MSB] ... 15 S5L9291X DIGITAL SIGNAL PROCESSOR DSP Command Command Address D7 DAC ATTN control 01011101 ($5D) DPLL control 1 10001000 ($88) DPLL control 2 10001001 ($89) DPLL control 3 10001010 ($8A) DPLL control 4 10001011 ($8B) DPLL control 5 10001100 ($8C) DPLL control 6 10001101 ($8D) Function control 10010000 ($90) Audio control 10010001 ($91) Frame sync control 10010010 ($92) Mode control 1 10010011 ($93) Mode control 2 10010100 ($94) CD Text 10010101 ($95) CLV gain control 10011000 ($98) CLV mode control 10011001 ($99) CLV control 1 10011010 ($9A) CLV control 2 10011011 ($9B) CLV control 3 10011100 ($9C) CLV control 4 10011101 ($9D) CLV control 5 10011110 ($9E) SOFFSET[7:0] Hi-Z SPLUS SDD PHASEDIV[1:0] SMOFFSET[3:0] Hi-Z POFFSET[7:0] Hi-Z LC PML SML[1:0] POS SGAIN[2:0] Hi-Z UN LOCK STRIO SMM [1:0] CLV IDLE PME SME PCKSEL[1:0] PGAIN[1:0] Hi-Z CDDSP PWDN MSCK SW GEQ SW OVSPL ESP PWDN DACCK SW GEQ2 SW WBN WPN LOCK HIGH PCEN OVSPL MS CM[3:0] /(PW64) WB EQ PWDN CLVCK SW DAC PWDNB Data D6 M4 D5 M3 D4 M2 D3 M1 D2 MO D1 SOFT ATTN WIDE INC3T PHASE GAIN REF98[1:0] DLF gain MAXTGAIN[1:0] CAPRANGE[1:0] ACC 3t CO1T CO2T D0 C MD DIRECT RETREF ISTAT Terminal Hi-Z M5 Hi-Z REF[1:0] Hi-Z DIVS1[1:0] DIVP1[5:0] Hi-Z DIVS2[1:0] DIVP2[5:0] Hi-Z DIVM2[7:0] Hi-Z C MD SPLIT CDROM PHASE ONLY FDEEM MRANGE[1:0] FSREG PLL TEST PLL PWRDN1 PLL PWRDN2 Hi-Z DEEM ERA OFF C1PNT C1PNT SW - JITM Hi-Z MUTE ZCMT ZDENL ATTN DAC MUTE V FLAG DATX MUTE DATX OEN S0S1 FSEL[1:0] WSEL[1:0] FSMD[1:0] SCS[1:0] LKFS ECLV ECLV PD NCLV CRCQ Hi-Z DATCK SW - RFCK SW - C4M SW JTFRV2 JTFRV1 Hi-Z - TEXT ON WP TEXT OUT GAIN Hi-Z Hi-Z 16 DIGITAL SIGNAL PROCESSOR S5L9291X DSP Command (Continued) Command Address D7 CLV Control 6 10011111 ($9F) 10Band EQ. Filter Gain Level(31Hz) 10Band EQ. Filter Gain Level(62Hz) 10Band EQ. Filter Gain Level(125Hz) 10Band EQ. Filter Gain Level(250Hz) 10Band EQ. Filter Gain Level(500Hz) 10Band EQ. Filter Gain Level(1kHz) 10Band EQ. Filter Gain Level(2kHz) 10Band EQ. Filter Gain Level(4kHz) 10Band EQ. Filter Gain Level(8kHz) 10Band EQ. Filter Gain Level(16kHz) 10EQ Volume Gain Control DATX & 1-bit DAC Control Output Port Control 1 Play Mode Control 10100000 ($A0) 10100001 ($A1) 10100010 ($A2) 10100011 ($A3) 10100100 ($A4) 10100101 ($A5) 10100110 ($A6) 10100111 ($A7) 10101000 ($A8) 10101001 ($A9) 10101010 ($AA) 10101110 A3($AE) 10101111 A9 ($AF) 11110000 ($F0) DS1 DS0 TALK[2:0] MNT HIZ PLAY SW DFCK RFCK OEN PLAY1 SBDT DUMB PLAY0 Hi-Z Hi-Z SC[1:0] SF[1:0] Hi-Z EQRST EQON VOLON EQVG[4:0] Hi-Z EQGB9[4:0] Hi-Z EQGB8[4:0] Hi-Z EQGB7[4:0] Hi-Z EQGB6[4:0] Hi-Z EQGB5[4:0] Hi-Z EQGB4[4:0] Hi-Z EQGB3[4:0] Hi-Z EQGB2[4:0] Hi-Z EQGB1[4:0] Hi-Z EQGB0[4:0] D6 D5 D4 Data D3 D2 D1 D0 CLV DFCT Hi-Z ISTAT Terminal Hi-Z 17 S5L9291X DIGITAL SIGNAL PROCESSOR ESP Write Command Command Address D7 MS control 10110000 ($B0) Data control 1 10110001 ($B1) Data control 2 10110010 ($B2) Data control 3 10110011 ($B3) Data control 4 1011_0100 ($B4) DRAM CTRL RAM TYPE RAM BANK RAM_BUS[1:0] RAM_SIZE[2:0] Hi-Z BBW (0) SBCEN WFF (0) MCP (1) ESP RESET JITB OFF SHOCK EN SBC[4:0] SHOCK SW CMD SHOCK Hi-Z Hi-Z MSWREN D6 MSWAC L DRAM SEL [1:0] D5 MSRDE N YFLGS YFCKP CMP12 DC COMP [1:0] Hi-Z D4 MSRACL Data D3 MSDCN2 D2 MSDCN1 D1 WAQV D0 MSON ISTAT Terminal Hi-Z ESP Read Command -I Command MS state 1 MS state 2 Address S7 10110101 ($B5) 10110110 ($B6) S6 S5 S4 FLAG6 MSEMP MSOVFL OVFL Data S3 S2 S1 MSWI H S0 MSRIH DCOMP ENCOD DECOD ESP Read Command - II Command MS data residual Address 10110111 ($B7) Data R[15:0] AM[21:6] 18 DIGITAL SIGNAL PROCESSOR S5L9291X MICOM DRAM Write Command Command DRAM Access 0 DRAM Access 1 DRAM Access 2 DRAM Access 3 Address D1 10111010 ($BA) 10111011 ($BB) 10111100 ($BC) 10111101 ($BD) MWR D2 MRD D3 D4 MAD[7:0] WRDATA[15:8] WRDATA[7:0] Data D5 D6 D7 D8 MAD[11:8] ISTAT Terminal Hi-Z Hi-Z Hi-Z Hi-Z MICOM DRAM READ COMMAND Command DRAM Access Read Data Address D1 D2 D3 D4 Data D5 D6 D7 D8 RDDATA[15:0] 10111111 ($BF) 19 S5L9291X DIGITAL SIGNAL PROCESSOR $5D Command Digital attenuation level control Command DAC ATTN control Address D7 01011101 ($5D) M5 D6 M4 D5 M3 D4 M2 Data D3 M1 D2 M0 D1 SOFT ATTN D0 CMD DIRECT MDAT MSB LSB Attenuation Level (dB) MSB MDAT LSB Attenuation Level (dB) M5 M4 M3 M2 M1 M0 M5 M4 M3 M2 M1 M0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -0.28 -0.42 -0.56 -0.71 -0.86 -1.01 -1.16 -1.32 -1.48 -1.64 -1.80 -1.97 -2.14 -2.32 -2.50 -2.68 -2.87 -3.06 -3.25 -3.45 -3.66 -3.87 -4.08 -4.30 -4.53 -4.76 -5.00 -5.24 -5.49 -5.75 -6.02 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -6.30 -6.58 -6.88 -7.18 -7.50 -7.82 -8.16 -8.52 -8.89 -9.28 -9.68 -10.10 -10.55 -11.02 -11.51 -12.04 -12.60 -13.20 -13.84 -14.54 -15.30 -16.12 -17.04 -18.06 -19.22 -20.56 -22.14 -24.08 -26.58 -30.10 -36.12 - 20 DIGITAL SIGNAL PROCESSOR S5L9291X SOFT ATTN Enable soft attenuation. The attenuation level is divided into 64 steps. SOFT ATTN 23.2ms 0 dB set1 set2 set3 set4 dB < Soft Attenuation Operation > 8 set5 smoothly directly set6 CMD DIRECT (option) L : Attenuate the 1-bit DAC using the soft attenuation block. H : Apply direct attenuation level to the 1-bit DAC without using the soft attenuation block. This disables the soft attenuation. 21 S5L9291X DIGITAL SIGNAL PROCESSOR $88 Command (Default Values D[7:0] = 0000 0000) Digital PLL control Command DPLL control 1 Address D7 10001000 ($88) WIDE Data D6 INC3T D5 PHASE GAIN D4 DLF GAIN D3 ACC3t D2 CO1T D1 CO2T D0 RETREF Bit D7 D6 D5 D4 D3 D2 D1 D0 Name WIDE INC3T PHASE_GAIN DLF_GAIN ACC3t CO1T CO2T RETREF DATA = 0 Normal Normal 1/2t 1/2^10 ignore 3t Normal Normal 1.1% Data = 1 Wide New 1t 1/2^9 accept 3t 1T correction 2T correction 2.3% Comment Wide mode Select 3T frequency error application Phase Adjust selection (option) Digital Loop Filter Gain selection ROM coefficient selection 1T 3T correction 2T 3T correction reference when return to M1 = 98 $89 Command (Default Value D [7:0] = 1111 0000) Digital PLL control Command DPLL control 2 Address D7 10001001 ($89) D6 D5 D4 REF98[1:0] REF[1:0] Data D3 D2 D1 D0 MAXTGAIN[1:0] CAPRANGE[1:0] Bits D[7:6] D[5:4] D[3:2] D[1:0] Name REF98[1:0] REF[1:0] MAXTGAIN[1:0] CAPRANGE[1:0] Data = 00 Data = 01 Data = 10 Data = 11 1.7% 1.7% 1 50% 2.3% 2.3% 1/2 40% 3.4% 3.4% 1/4 30% 4.6% 4.6% 1/8 20% Comment Outward reference when M1 = 98 Outward reference when M1 98 MAX T accumulation gain Capture range selection 22 DIGITAL SIGNAL PROCESSOR S5L9291X $8A Command (Default Values D [7:0] = 0101 0110) Digital PLL control Command DPLL control 3 Address D7 10001010 ($8A) D6 D5 D4 DIVS1[1:0] Data D3 D2 D1 D0 DIVP1[5:0] Bits D[7:6] Name DIVS1[1:0] Data = 00 Data = 01 Data = 10 Data = 11 1 1/2 1/4 1/8 Comment PLL1 post scaler Bits D[5:0] Name DIVP1[5:0] Data = 000000 - 111111 0 - 63 Comment PLL1 pre divider $8B Command (Default Value D [7:0] = 1001 0110) Digital PLL control Command DPLL control 4 Address D7 10001011 ($8B) D6 D5 D4 DIVS2[1:0] Data D3 D2 D1 D0 DIVP2[5:0] Bits D[7:6] Name DIVS2[1:0] Data = 00 Data = 01 Data = 10 Data = 11 1 1/2 1/4 1/8 Comment PLL2 post scalar Bits D[5:0] Name DIVP2[5:0] Data = 000000 - 111111 0 - 63 Comment PLL2 pre divider $8C Command (Default Values D [7:0] = 0101 0000) Digital PLL Control Command DPLL control 5 Address D7 10001100 ($8C) D6 D5 D4 Data D3 D2 D1 D0 DIVM2[7:0] Bits D[7:0] Name DIVM2[7:0] Data = 00000000 - 11111111 0 - 255 Comment PLL2 main divider 23 S5L9291X DIGITAL SIGNAL PROCESSOR $8D Command (Default Values D [7:0] = 0000 0000) Digital PLL control Command DPLL control 6 Address D7 10001101 ($8D) CMD SPLIT D6 PHASE ONLY D5 D4 MRANGE[1:0] Data D3 FSREG D2 PLL TEST D1 D0 PLL PLL PWRDN1 PWRDN2 CMD_SPLIT (option) The digital PLL control micom command is automatically applied when the speed is changed($F0) or at Jitter Free2($94). H : Each DPLL control Micom Commands ($8A, $8B, $8B) are applied using the Micom Interface terminals (MCK, MDAT, MLT). L : DPLL control Micom Command ($8A, $8B, $8B) is applied automatically inside. PHASE_ONLY (option) Controls phase compensation status at DPLL. H : Phase compensation L : Phase compensation + Frequency compensation MRANGE[1:0] Controls the range of the PLL1 Main Divider M value range Bits D[5:4] Name MRANGE[1:0] Data = 00 50% Data = 01 40% Data = 10 30% Data = 11 20% Comment Lock Range FSREG Verifies the Frame Sync status(|Thigh-Tlow| 1) at MAX T H : Verify L : Ignore PLLTEST PLL1 TEST mode H : TEST (M1<=M2), PLL PWDN1 PLL1 Power Down mode H : Power Down, PLL PWDN2 PLL2 Power Down mode H : Power Down, L : Normal L : Normal L : Normal 24 DIGITAL SIGNAL PROCESSOR S5L9291X $90 Command DSP Function Control (Default Values D [7:0] = 0000 0000) DSP Function Control Command Function control Address D7 10010000 CDROM ($90) D6 FDEEM D5 DEEM D4 ERA OFF Data D3 C1PNT D2 C1PNT SW D1 D0 JITM CDROM H: CDROM mode (Interpolation off) L: CDP mode (Interpolation on) FDEEM, DEEM De-Emphasis Automatic control and compulsion control select FDEEM 0 0 1 1 DEEM 0 1 0 1 De-emphasis on/off Off On/Off Off On - Comment Automatic operate to detect emphasis signal of subcode information Operate without regard to emphasis signal of subcode information ERA_OFF: H: Erasure correction off L: Erasure correction on C1PNT : C1 2 Error correction C1 pointer set/reset control H: C1PNT = reset L: C1PNT = set C1PNT_SW: C1PNT set/reset command input method control H: TESTV terminal use L: Micom command use C1PNT (option) Mute SRAM Address copy permission (Write base count copy from read base counter) H: Accept L: Reject 25 S5L9291X DIGITAL SIGNAL PROCESSOR $91 Command (Default Values D [7:0] = 1000 1000) Control of each function related to audio data Command Audio control Address D7 10010001 ($91) MUTE D6 ZCMT D5 ZDENL D4 ATTN Data D3 DAC MUTE D2 VFALG D1 DATX MUTE D0 DATX OEN MUTE DSP Mute Enable Signal H : DSP MUTE On L : DSP MUTE Off ZCMT DSP Zero Cross Mute Enable Signal (Valid when MUTE On) H : DSP Zero Cross Mute On, L : DSP Zero Cross Mute Off ZDENL Zero Detection Mute Disable H : Disable ATTN DSP Attenuation Control H : DSP Attenuation On L : Enable L : DSP Attenuation Off DAC MUTE Sets 1-bit DAC Block input data to 'L'. H : DAC MUTE On, L : DAC MUTE Off VFALG DATX Block Input V-bit Control H : Set to 'L' L : C2PO DATX_MUTE Sets Digital Audio Interface Block Input Data to 'L'. H : DATX MUTE On L : DATX MUTE Off DATX_OEN DATX Output function enable. H : Enable L : Disable 26 DIGITAL SIGNAL PROCESSOR S5L9291X $92 Command (Default Values D [7:0] = 0000 0000 ) Control of functions related to frame sync Command Frame sync control Address D7 10010010 ($92) D6 D5 D4 FSEL[1:0] WSEL[1:0] Data D3 D2 D1 D0 FSMD[1:0] SCS[1:0] FSEL[1:0]: Control of cycle for frame sync protection and insertion FSEL[1:0] 00 01 10 11 WSEL[1:0]: Control of window size related to frame sync protection WSEL[1:0] 00 01 10 11 FSMD: [1:0] Frame sync detection method control FSMD [1:0] 00 01 10 11 SCS[1:0] Subcode Sync S0S1 Select SCS[1:0] 00 01 10 11 S0S1 (PAD or ESP) S0 or S1 Windowed S0 or S1 Windowed S0 and S1 Windowed S0 and S1 SQOK Sync (to Subcode) S0 or S1 S0 or S1 S0 and S1 Windowed S0 and S1 Detection Method Pattern Compensation Cycle 1 Cycle 2 11t - 11t 11t - 11t, 10 - 12t, 12t - 10t 10t - 11t, 11t - 12t, 11t - 11t, 11t - 10t, 12t - 11t cycle 1, 10t - 12t, 12t - 10t Comment Window Size(t) 3 7 13 26 Control Cycle (Frame) 2 4 8 13 27 S5L9291X DIGITAL SIGNAL PROCESSOR $93 Command (Default Values D [7:0] = 0010 0001) Control of modes of functions in DSP Command Mode control 1 Address D7 10010011 ($93) CDDSP PWDN D6 ESP PWRDN D5 EQ PWDN D4 DAC PWDNB Data D3 ECLV D2 ECLV PD D1 NCLV D0 CRCQ CDDSP_PWDN CDDSP Function Power Down H : Power Down, ESP_PWDN ESP function Power Down H : Power Down On, L : Power Down Off L : Power Down Off EQ_PWDN EQ(Equalizer) Function Power Down H : Power Down, L : Power Down Off DAC_PWDNB 1-bit DAC Function Power Down H : Power Down Off, L : Power Down ECLV Emergency CLV Servo, Overflow prevention H : Repeat output of H, Hi-Z, and L at a regular cycle through the SMDP terminal L : normal operation ECLV_PD SMDP output cycle control at ECLV H: Bottom Hold cycle (Refer to $98) L : Peak Hold cycle (Refer to $98 ) NCLV H : CLV phase servo driven by frame sync L : CLV phase servo driven by base counter CRCQ L : SQDT without SQOK H : SQDT with SQOK (If S0S1 is 'H', SQDT = SQOK) 28 DIGITAL SIGNAL PROCESSOR S5L9291X $94 Command (Default Values D [7:0] = 0000 0000 ) Control of function modes in DSP Command Mode control 2 Address D7 10010100 ($94) MSCK SW D6 DACCK, SW D5 CLVCK SW D4 DATCK SW Data D3 RFCK SW D2 C4M SW D1 JTFRV2 D0 JTFRV1 Bit {D7,D6} Value 1x 01 00 1-Bit DAC Master Clock Input to RFCK terminal for external clock source $A9 D1(RFCK_OEN) is always "L". VCO2(PLL Block Clock) X'tal Bit D5 D4 D3 D2 D1 D0 Name CLVCK_SW DATCK_SW RFCK_SW C4M_SW JTFRV2 JTFRV1 Data = 0 X'tal X'tal X'tal/VCO X'tal X'tal X'tal Data = 1 VCO2 VCO2 X'tal VCO2 VCO2 VCO1 Comment Fixed X'tal or variable X'tal conversion Fixed X'tal or variable X'tal conversion Use RFCK clock in CLV servo processing according to jitter free mode Fixed X'tal or variable X'tal conversion Use the variable VCO2 clock in data processing according to VCO1 Use VCO1 clock in data processing 29 S5L9291X DIGITAL SIGNAL PROCESSOR $95 Command (Default Values D[7:0] = 0000 0000) Control of CD Text mode Command CD TEXT Address D7 10010101 ($95) GEQ SW D6 GEQ2 SW D5 D4 Data D3 D2 D1 TEXT ON D0 TEXT OUT GEQ_SW,GEQ2_SW Bit {D7,D6} Value 00 10 X1 GEQ Master Clock DACCK_SW == 0 XI*2/3(11MHz) XI(16.9344MHz) Input to RFCK terminal for external clock source $A9 D1(RFCK_OEN) is always "L" DACCK_SW == 1 VCO2*2/3 GEQ Power Optimization Command Value Sampling Frequency $94 $95 {D7,D6} {D7,D6} CDDSP 44.1kHz 00 00 External Audio Source(Ex:MP3) 32kHz 10 01 44.1kHz 00 00 48kHz 10 10 TEXTON CD Text Function On/Off Signal. H : CD Text Function Enable, L : CD Text Function Disable TEXTOUT CD TEXT Information Output Control On/Off Signal H : SQDT with signal CD-Text information transmission Enable, L : Disable 30 DIGITAL SIGNAL PROCESSOR S5L9291X $98 Command (Default Values D [7:0] = 0000 0111) Control cycle and gain control in CLV speed mode Command CLV gain control Address D7 10011000 ($98) OVSPL D6 WBN D5 WPN D4 LOCK HIGH Data D3 OVSPL MS D2 WB D1 WP D0 GAIN OVSPL (option) Over sampling of CLV output (SMDP, SMDS) cycle by 7.35kHz * 4 and output. H : Over-sampling Enable L : Over-sampling Disable WBN (option) CLV speed mode Bottom Hold cycle control H : RFCK/64 L : determined by WB WPN (option) CLV speed mode Peak Hold cycle control H : RFCK/8 L : determined by WP LOCK_HIGH LOCK PAD as 'H' while Command is input. H : LOCK High L : Normal Lock OVSPL_MS (option) Over-sampling Enable SMDS Output Mode Select H : PWM (H, L) L : Tri-State (H, Hi-Z, L) WB CLV speed mode Bottom Hold Cycle Control H : RFCK/16 L : RFCK/32 WP CLV speed mode Peak Hold Cycle Control H : RFCK/2 L : RFCK/4 {WPN,WP} 00 01 10 11 Control Cycle RFCK/4 RFCK/2 RFCK/8 1RFCK/8 {WBN,WB} 00 01 10 11 Control Cycle RFCK/32 RFCK/16 RFCK/64 RFCK/64 GAIN CLV speed mode SMDS Output GAIN Control H : 0dB L : -12dB 31 S5L9291X DIGITAL SIGNAL PROCESSOR $99 Command (Default Values D [7:0] = 0000 0000 ) CLV mode control Command CLV mode control Address D7 10011001 ($99) D6 D5 CLV IDLE D4 PCEN UNLOCK [1:0] Data D3 D2 D1 D0 CM[3:0] UNLOCK[1:0] unlock cycle control UNLOCK[1:0] 00 01 10 11 Function If LKFS can remain at 'L' for 128 frames, the LOCK is 'L'. If LKFS can remain at 'L' for 96 frames, the LOCK is 'L'. If LKFS can remain at 'L' for 192 frames, the LOCK is 'L'. If LKFS can remain at 'L' for 224 frames, the LOCK is 'L'. CLV_IDLE Use to place CLV servo control in idle mode. (Set POS ($9B) to 'H') H : Output a specific error ($9E, SOFFSET[7:0])to the SMDS terminal, IDLE mode. L : Normal Mode PCEN Phase Error Masking status determination when setting the dead zone. H : SMDP Phase Error Masking Enable. (When WFCK frequency Error has entered the Dead Zone) L : SMDP Phase Error Masking Disable. CM[3:0] CLV Servo Control Mode Setting Mode Forward (KICK) Reverse (BRAKE) High speed (CLV-H) Speed (CLV-S) Phase (CLV-P) XPHSP (CLV-A) CM[3:0] 1000 1010 1100 1110 1111 0110 SMDP H L Speed Speed Phase Speed Phase Speed Phase L SMDS Hi-Z Hi-Z Hi-Z Hi-Z Phase Hi-Z Phase Hi-Z Phase Hi-Z SMEF L L L L Hi-Z L Hi-Z L Hi-Z L SMON H H H H H H Function Spindle motor forward mode Spindle motor reverse mode Rough servo mode at jump Rough servo mode at start up PLL servo mode Normal play mode (When LOCK is 'H', CLV-P operation and when 'L', CLV-S operation ) Automatic servo mode (When LOCK is 'H' or GFS is 'H', operate in CLV-P, but others, operate in CLV-S') Spindle motor stop mode VPHSP (CLV-A) 0101 H Stop (STOP) 0000 L 32 DIGITAL SIGNAL PROCESSOR S5L9291X $9A Command (Default Values D [7:0] = 0000 0000) Digital CLV control Command CLV control 1 Address D7 10011010 ($9A) STRIO D6 SMM D5 PME D4 SME Data D3 D2 D1 D0 PCKSEL[1:0] PGAIN[1:0] STRIO: Tri-state out enable in phase mode H: Tri-state L: PWM SMM: SMDS mask limit manual setting enable H: Manual setting L: Auto setting PME: SMDP mask enable H: Mask enable L: Mask disable SME SMDS mask enable (dead zone enable) H: Mask enable L: Mask disable PCKSEL[1:0]: MDP resolution clock selection Bits D[3:2] Name PCKSEL [1:0] Data = 00 CLK4M_ CLV/2 Data = 01 CLK4M_ CLV/4 Data = 10 CLK4M_ CLV/8 Data = 11 CLK4M_ CLV/16 Comment MDP resolution clock selection PGAIN: SMDP gain setting Bits D[1:0] Name PGAIN[1:0] Data = 00 1 Data = 01 1/2 Data = 10 1/4 Data = 11 1/8 Comment MDP gain selection 33 S5L9291X DIGITAL SIGNAL PROCESSOR $9B Command (Default Values [7:0] = 0000 0010) Digital CLV control Command CLV control 2 Address D7 10011011 ($9B) LC D6 PML D5 D4 SML[1:0] Data D3 POS D2 D1 SGAIN[2:0] D0 LC: Lock control H : 1x 2x or 2x 1x then LOCK is forced to 0 L : Normal LOCK control PML : SMDP mask limit H : SMDP mask for SMDS error center value 50% L : SMDP mask for SMDS error center value 25% SML: MDS mask limit (dead zone area) at MDS error center value Bits D[5:4] Name SML[1:0] Data = 00 0% Data = 01 6.25% Data = 10 12.5% Data = 11 25% Comment Dead zone selection When it enters the dead zone around the data rate, the MDS error value is output as 0. This minimizes the change in plus(+) and minus(-) frequently generated in the reference data rate and reduces the number of times required for motor control to reduce power consumption. The phase control also turns off in this dead zone. POS: MDP output selection H: Gain controlled SMDP L: Normal SMDP SGAIN: SMDS gain setting SGAIN[2:0] 000 001 010 011 100 101 110 111 Gain Value 1 2 4 8 16 32 64 128 34 DIGITAL SIGNAL PROCESSOR S5L9291X $9C Command (Default Values D [7:0] = 0000 0000) Digital CLV control Command CLV control 3 Address D7 10011100 ($9C) D6 D5 D4 Data D3 D2 D1 D0 POFFSET[7:0] POFFSET[7]:SMDP offset sign H: Minus (-) L: Plus (+) POFFSET[6:0]: SMDP offset absolute value $9D Command (Default Values D [7:0] = 0000 0000 ) Digital CLV control Command CLV control 4 Address D7 10011101 ($9D) SPLUS D6 SDD D5 D4 PHASEDIV[1:0] Data D3 D2 D1 D0 SMOFFSET[3:0] SPLUS: SMDS offset plus enable H: Enable L: Disable SDD: SMDS speed down control disable H: Speed down control disable L: Speed down control enable PHASEDIV[5:4]: Phase comparator period setting Bits D[5:4] Name PHASEDIV [1:0] Data = 00 Data = 01 Data = 10 Data = 11 RFCK/2 RFCK/4 RFCK/8 RFCK/16 Comment Phase comparator period selection SMOFFSET[3:0]:SMDS mask limit value 0000 - 1111 35 S5L9291X DIGITAL SIGNAL PROCESSOR $9E Command (Default Values D [7:0] = 0000 0000) Digital CLV control Command CLV control 5 Address D7 10011110 ($9E) D6 D5 D4 Data D3 D2 D1 D0 SOFFSET[7:0] SOFFSET[7:0]: SMDS offset Output the final error which add the SOFFSET in SMDS error when SPLUS is "1" $9F Command (Default Values D[7:0]:=0000 0000) Control of function modes in DSP Command CLV control 6 Address D7 10011111 ($9F) D6 D5 D4 Data D3 D2 D1 D0 CLV DFCT CLV_DFCT If EFM Pulse Width is greater than 64T, the signal is indicates DEFECT and SMDP and SMDS outputs are set to hi-z so, it (ED: what does "it" refer to?) does not control CLV. H : Defect detection control , L : Normal control 36 DIGITAL SIGNAL PROCESSOR S5L9291X $A0 Command (Default Values D[7:0]:=0000 0000) 10Band EQ. Filter Gain Control Command 10Band EQ. Filter Gain Control 1 Address D7 10100000 ($A0) D6 D5 D4 Data D3 D2 D1 D0 Filter Gain Level(31Hz) [ED: cannot understand what these sentences are saying.] $A1 Command (Default Values D[7:0]:=0000 0000) 10Band EQ. Filter Gain Control Command 10Band EQ. Filter Gain Control 2 Address D7 10100001 ($A1) D6 D5 D4 Data D3 D2 D1 D0 Filter Gain Level(62Hz) [4:0] is the level of Gain which is multiplied by Band1. $A2 Command (Default Values D[7:0]:=0000 0000) 10Band EQ. Filter Gain Control Command 10Band EQ. Filter Gain Control 3 Address D7 10100010 ($A2) D6 D5 D4 Data D3 D2 D1 D0 Filter Gain Level(125Hz) [4:0] it is the level of Gain that multiplied by Band2. 37 S5L9291X DIGITAL SIGNAL PROCESSOR $A3 Command (Default Values D[7:0]:=0000 0000) 10Band EQ. Filter Gain Control Command 10Band EQ. Filter Gain Control 4 Address D7 10100011 ($A3) D6 D5 D4 Data D3 D2 D1 D0 Filter Gain Level(250Hz) [4:0] is the level of Gain which is multiplied by Band3. $A4 Command (Default Values D[7:0]:=0000 0000) 10Band EQ. Filter Gain Control Command 10Band EQ. Filter Gain Control 5 Address D7 10100100 ($A4) D6 D5 D4 Data D3 D2 D1 D0 Filter Gain Level(500Hz) [4:0] is the level of Gain which is multiplied by Band4. $A5 Command (Default Values D[7:0]:=0000 0000) 10Band EQ. Filter Gain Control Command 10Band EQ. Filter Gain Control 6 Address D7 10100101 ($A5) D6 D5 D4 Data D3 D2 D1 D0 Filter Gain Level(1KHz) [4:0] is the level of Gain which is multiplied by Band5. $A6 Command (Default Values D[7:0]:=0000 0000) 10Band EQ. Filter Gain Control Command 10Band EQ. Filter Gain Control 7 Address D7 10100110 ($A6) D6 D5 D4 Data D3 D2 D1 D0 Filter Gain Level (2kHz) [4:0] is the level of Gain which is multiplied by Band 6. 38 DIGITAL SIGNAL PROCESSOR S5L9291X $A7 Command (Default Values D[7:0]:=0000 0000) 10Band EQ. Filter Gain Control Command 10Band EQ. Filter Gain Control 8 Address D7 10100111 ($A7) D6 D5 D4 Data D3 D2 D1 D0 Filter Gain Level (4kHz) [4:0] is the level of Gain which is multiplied by Band 7. $A8 Command (Default Values D[7:0]:=0000 0000) 10Band EQ. Filter Gain Control Command 10Band EQ. Filter Gain Control 9 Address D7 10101000 ($A8) D6 D5 D4 Data D3 D2 D1 D0 Filter Gain Level (8kHz) [4:0] is the level of Gain which is multiplied by Band 8. $A9 Command ( Default Values D [7:0] = 0000 0000 ) 10Band EQ. Filter Gain Control Command 10Band EQ. Filter Gain Control 10 Address D7 10101001 ($A9) D6 D5 D4 Data D3 D2 D1 D0 Filter Gain Level (16kHz) [4:0] is the level of Gain which is multiplied by Band 9. 39 S5L9291X DIGITAL SIGNAL PROCESSOR $AA Command (Default Values D[7:0] = 1000 0000) Volume Gain Control Command Volume Gain Control Address D7 10101010 ($AA) EQRST D6 EQON D5 VOLON D4 Data D3 D2 D1 D0 Volume Gain Control D[7] : band equalizer reset L : reset enable H : reset disable D[6] : band equalizer on/off H : on L : off D[5] : digital volume only mode on/off H : on (no band equalization) L : off D[4:0] Volume Gain must be input from 0 to 31.The actual gain value is inside the IC, and the MICOM controls the volume level according to the proper input value. 40 DIGITAL SIGNAL PROCESSOR S5L9291X $AE Command (Default Values D[7:0]:=0000 0000) 1-Bit DAC Mode Control Command 1-Bit DAC Control Address D7 10101110 ($AE) D6 D5 D4 Data D3 D2 D1 SF[1:0] D0 SC[1:0] SF[1:0] 1-Bit DAC & DATX Sampling Frequency Control In the Control Status Data, it controls the Sampling Rate(bit24 - bit27) from Digital Audio output signal(DATX) SF[1:0] 00 01 11 Others SC[1:0] Calibration Range Scale Control Bits D[1:0] Name SC[1:0] Data=00 X1 Data=01 X2 Data=10 X4 Data=11 X0.5 Comment Zero Detection Mute used Available Audio Sampling Frequency 44.1 kHz 48 kHz 32 kHz Reserved 41 S5L9291X DIGITAL SIGNAL PROCESSOR $AF Command (Default Values D[7:0] = 0000 0000) Output Signal On/Off Control and Monitor Output Signal Selection Command Output Port Control 1 Address D7 10101111 ($AF) D6 D5 TALK[2:0] D4 Data D3 MNT HIZ D2 D1 RFCK OEN D0 SBDT DUMB TALK[2:0] Monitoring Terminal Output Selection Bit Name TALK[2:0] 000 001 010 011 100 101 110 111 MNT5 0 FSYNC FSYNC DAC_SADT Fchange DIVN1[5] DAC_SADT FLAG6 MNT4 0 EFMFLAG FSDW DAC_LRCK DIVN98 DIVN1[4] DAC_LRCK SHOCK STATUS Output Description MNT3 0 ECFL3 ULKFS DAC_BCK DIVNFAST DIVN1[3] DAC_BCK OVFL MNT2 0 ECFL2 EMPH ESP_BCK AT2T DIVN1[2] DSP_BCK EMPTY MNT1 0 ECFL1 SQOK ESP_LRCK EFMIN DIVN1[1] DSP_LRCK DCOMP MNT0 0 ECFL0 TIM2 ESP_SADT EFMOUT DIVN1[0] DSP_SADT MATCH Signal Name DAC_LRCK, DAC_BCK, DAC_SADT DSP_LRCK, DSP_BCK, DSP_SADT ESP_LRCK, ESP_BCK, ESP_SADT MNT_HIZ H : MNT[2:0] Hi-Z Output (Input mode) L : MNT[2:0] Normal Output RFCK_OEN H : RFCK output, SBDT DUMB H : Output Off, ESP Off(X1 - X2) X1 - X2 X1 - X2 - ESP On(X1 - X2) X1 X1 - X2 X1 Comment DSP Output, DAC Input DSP Output ESP Output L : RFCK input L : Output On 42 DIGITAL SIGNAL PROCESSOR S5L9291X $B0 Command ( Default Values D [7:0] = 0000 0000 ) ESP memory system setting Command MS control Address D7 D6 D5 D4 MSRAC L 10110000 MSWRE MSWAC MSRDE ($B0) N L N Data D3 MSDCN 2 D2 MSDCN 1 D1 WAQV D0 MSON MSWREN: Memory system write enable (ADPCM encoding on/off) H: Write enable L: Write disable MSWACL: Memory system write address clear H: Clear enable L: Clear disable MSRDEN: Memory system read enable (ADPCM decoding on/off) H: Read enable L: Read disable MSRACL: Memory system read address clear H: Clear enable L: Clear disable MSDCN2, MSDCN1: Memory system data compare/connection control MSDCN2 0 0 1 1 WAQV: Q data valid H: Valid L: Invalid MSON: Memory system on/off (ESP on/off) H: On L: Off MSDCN1 0 1 0 1 Mode Connection operation disable Direct connection 2-pair connection 3-pair connection 43 S5L9291X DIGITAL SIGNAL PROCESSOR $B1 Command ( Default Values D [7:0] = 0000 0000 ) Command Data control 1 Address D7 10110001 ($B1) D6 D5 YFLGS D4 YFCKP Data D3 CMP12 D2 D1 D0 COMP [1:0] YFLGS, YFCK JITB Signal Input Conditional Control YFLGS 0 0 1 1 CMP12: 12/16 bits comparison connection H: 12-bit comparison connection L: 16-bit comparison connection COMP[1:0] Encoded data comparison mode control Comp [1:0] 00 01 10 11 4-bit comparison 5-bit comparison 6-bit comparison Full bits comparison Mode YFCLK 0 1 0 1 Mode RFCK input negative edge, JITB = 'L' RFCK input positive edge, JITB = 'L' JITB = 'L' JITB = 'H' 44 DIGITAL SIGNAL PROCESSOR S5L9291X $B2 Command (Default Values D[7:0] = 0000 0000) Command DATA Control 2 Address D7 10110010 ($B2) BBW D6 WFF D5 MCP D4 ESP RESET Data D3 JITB OFF D2 SHOCK EN D1 SHOCK SW D0 CMD SHOCK BBW BlkCk(S0S1) Blocking Signal From WAQV. H : Blocking L : No Blocking . WFF WAQV Forced falling signal within a particular region. H : No Forced Falling. L : Forced Falling. MCP Repeat Sound Mis-Connection Protect. H : Protect. L : No Protect. ESP RESET ESP Block Reset while at 'H'. H : All ESP Block Reset. L : Normal JITB_OFF JITB signal is not used for shock processing. H : JITB signal not used. L : JITB signal used. SHOCK_EN Determines whether the external input shock sense signal (SBCK) and Micom Command SHOCK sense signal(CMD_SHOCK) should be used at shock processing H : Use SHOCK sense signal (Use SBCK lead when using external signal) L : Not use SHOCK sense signal. SHOCK_SW Determines whether to use the SHOCK sense signal should be used as an external lead or as an internal Micom command. H : Use as external lead(SBCK) L : Use as internal Micom Command(CMD_SHOCK) CMD_SHOCK Internal SHOCK sense signal H : SHOCK generation L : SHOCK not generated 45 S5L9291X DIGITAL SIGNAL PROCESSOR $B3 Command (Default Values D[7:0] = 0000 0000) Command DATA Control 3 Address D7 10110011 SBC EN ($B3) D6 D5 D4 Data D3 D2 SBC[4:0] D1 D0 SBC EN: SQOK Bad Count Setting Enable BlkCk(S0S1) Blocking Signal From WAQV. H : Enable L : Not Enable. SBC: SQOK Bad Count Setting Value := SBC * 2 a Shock $B4 Command (Default Values D[7:0] = 1000 0000) Command DATA Control 4 Address D7 10110100 ($B4) DRAM CTRL D6 RAM TYPE D5 RAM BANK D4 Data D3 D2 D1 RAM_SIZE[2:0] D0 RAM_BUS[1:0] DRAMCTRL DRAM CTRL On/Off Control H : DRAM CTRL On L : DRAM CTRL Off RAM[6:0] RAM_TYPE 0 : EDO DRAM 1 : SDRAM RAM_BANK 0 : 2 Bank (c)c 1 : 4 Bank (c)c RAM_BUS[1:0] 00 : x4 (c)e 01 : x8 10 : x16 11 : X16(Reserved) RAM_SIZE[2:0] 000 : 4M (c)e 001 : 16M 010 : 32M(16M 2EA) (c)c 011 : 64M 100 : 128M 101 : 128M(64M 2EA) 110 : 256M 111 : 256M(128M 2EA) 1) SDRAM Only, 2) EDO DRAM Only * 2 Bank in the SDRAM is consist in only 16M and 64M. 46 DIGITAL SIGNAL PROCESSOR S5L9291X $B5 Command (Default Values D [7:0] = 0000 0000) Command MS state 1 Address S7 10110101 ($B5) S6 S5 S4 FLAG6 MSOVFL Data S3 S2 S1 MSWI H S0 MSRIH M7-M0 DCOMP FLAG6: JITB signal, Reset after $B5H status read. H: Jitter margin overflow MSOVFL: Memory system overflow pulse, reset after $B5H status read. H: Write overflow DCOMP: Data compare/connection operation H: Compare/connection operating now MSWIH: Encoding sequence stop due to internal states H: Encoding stop MSRIH: Decoding sequence stop due to internal states, reset after $B5H status read. H: Decoding stop $B6 Command (Default Values D [7:0] = 0000 0000) Command MS state 2 Address S7 10110110 ($B6) S6 S5 OVFL S4 MSEMP Data S3 S2 S1 S0 M7-M0 ENCOD DECOD MSEMP: Valid data empty state H: Invalid (when RA exceed VWA) L: Valid OVFL: Write overflow state H: Memory full ENCOD: Encoding sequence operating state H: Encoding now DECOD: Decoding sequence operating state H: Decoding now 47 S5L9291X DIGITAL SIGNAL PROCESSOR $B7 Command Memory system valid data residual Command MS data residual R[15:0] := Valid Data Accumulated VWA-RA Anti-shock memory valid data residual Bit X4 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 64M Bits 32M Bits 16M Bits 8M Bits 4M Bits 2M Bits 1M Bits 512K Bits 256K Bits 128K Bits 64K Bits 32K Bits 16K Bits 8K Bits 4K Bits Function X8 128M Bits 64M Bits 32M Bits 16M Bits 8M Bits 4M Bits 2M Bits 1M Bits 512K Bits 256K Bits 128K Bits 64K Bits 32K Bits 16K Bits 8K Bits 4K Bits 128M Bits 64M Bits 32M Bits 16M Bits 8M Bits 4M Bits 2M Bits 1M Bits 512K Bits 256K Bits 128K Bits 64K Bits 32K Bits 16K Bits 8K Bits X16 Address 10110111($B7) Data R[15:0] 48 DIGITAL SIGNAL PROCESSOR S5L9291X $BA - $BD Command Write Data From Micom To External DRAM Command DRAM Access 0 DRAM Access 1 DRAM Access 2 DRAM Access 3 Address D7 10111010 ($BA) 10111011 ($BB) 10111100 ($BC) 10111101 ($BD) MWR D6 MRD D5 D4 MAD [7:0] WRDATA [15:8] WRDATA [7:0] Data D3 D2 D1 D0 MAD(11:8) ISTAT Terminal Hi-Z Hi-Z Hi-Z Hi-Z MWR Sign bit for writing the datum of WRDATA[15:0] to DRAM MAD[11:0] address H : Write Enable Reset after writing to DRAM MRD Storing in RDRDATA[15:0] after datum reading from DRAM MAD[11:0] address H : Read Enable Reset after writing to DRAM MAD[11:0] DRAM Read/Write Address WRDATA[15:0] DRAM Write Data 49 S5L9291X DIGITAL SIGNAL PROCESSOR BF Command Write Data From External DRAM to MICOM Command DRAM Access Read Data RDDATA[15:0] DRAM Read Data Address 1011_1111 ($BF) Data D[15:0] RDDATA[15:0] 50 DIGITAL SIGNAL PROCESSOR S5L9291X $F0 Command ( Default Values D [7:0] = 0000 0000 ) Data processing speed control Command Play mode control Address D7 11110000 ($F0) DS1 D6 DS0 D5 D4 Data D3 PLAY SW D2 DFCK D1 D0 PLAY[1:0] DS1, DS0 X1, X2 speed control DS1 0 1 DS0 0 1 Mode 1X 2X PLAY_SW Normal Play Mode change by external TEST Pin or Micom Command This function can be enabled only when TEST[3] Pin is `L'. L : TEST Pin control H : Micom Command control DFCK 1-bit DAC speed control H : 2X, L : 1X PLAY1, PLAY0 Normal Play Mode Bit Name PLAY[1:0] 00 01 10 11 TEST Pin TEST[3:0] 0000 0001 0010 0011 Normal 1 Normal 2 Normal 3 Normal 4 Serial Audio Data Interface impossible Serial Audio Data Interface impossible, (3-Band EQ is OFF) Serial Audio Data Interface possible (Audio Out Block Data Output) Serial Audio Data Interface possible (ESP Block Data ) MODE Comment 51 S5L9291X DIGITAL SIGNAL PROCESSOR EFM DEMODULATION EMF block is a circuit, which demodulates the EMF signal read from the disc, and is composed of the frame sync detection circuit and the control signal generator circuit. EFM Demodulation When the modulated 14 channel bit data is input, they are demodulated to 8 bit data. The demodulated data are classified into two types, the subcode data and audio data. The subcode data is input to the subcode processing block and the audio data is stored in the internal SRAM, after which it is corrected for error. Frame Sync Detection/Protection/Insertion Frame sync detection The data is configured in the unit of frames, of which frame sync, subcode data, audio data, redundancy data are configured in one frame. The frame sync is detected because it is used as the reference signal to synchronize the data output from the frame sync for extracting correct data. (Related Command Register: $92, FSMD [1:0]) Frame sync protection/insertion Frame sync may be detected in data besides that of frame sync or omitted due to effects from disc defects or jitters etc. In such cases, frame sync must be protected and inserted. A window must be made according to the $92 command register's WSEL[1:0] to protect frame sync. The data that enter this frame syn is the valid data and the frame sync that exits this window is ignored. If frame sync is not detected in the frame sync protection window, the frame sync made in the internal counter is inserted. If frame sync is inserted continuously to reach the number of frames specified by FSEL[1:0] of the $92 command register, the frame sync protection window is ignored as ULKFS becomes `H' and the following frame sync detected is immediately accepted. If the frame sync is accepted, ULKFS signal becomes "L" to accept the frame sync detected in the window. 52 DIGITAL SIGNAL PROCESSOR S5L9291X SUBCODE The subcode sync signal SOS1 is detected in the subcode sync block. After SO is detected, S1 is detected after one frame passes. At this time, SO+S1 signal is output through the SOS1 terminal, and SOS1 signal is output through the SBDT terminal when the SOS1 signal is ` H'. Of the data input to the EFMI terminal, 14-bit subcode data is EFM demodulated, synchronized with the WFCK signal to become 8-bit (P, Q, R, S, T, U, V, W) subcode data and output as SBDT through the SBCK clock. Of the 8 subcode data, only Q data is selected and saved in 80 shift registers using the WFCK signal. The CRC results of the stored data are synchronized to the S0S1 positive edge and output through the SQOK. If the CRC results are error, `L' is output to the SQOK terminal and, if not, `H' is output. If CRCQ's $93 command register is `H', CRC results are output through the SQDT terminal from the interval that SOS1 is `H' to the negative edge of SQCK. The following illustrates the timing diagram of the subcode block. SQCK, SQDT, S0S1 Timing Relationship SOS1 SQOK SQCK ~ ~ ~ ~ ~ ~ ~ ~ SQDT (CRCQ=1) SQDT (CRCQ=0) SQOK(n) Q4 0 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q8 Q8 Q7 Q7 Q6 Q6 Q5 Q5 Q80 Q79 Q78 Q80 Q79 Q78 Q77 Q77 SQOK(n+1) Q4 0 Q4 NOTE: If CRCQ of the subcode-Q data is `H', SQOK signal is output through SQDT according to the SQCK signal and, if CRCQ is `L', SQOK signal is not output through SQDT. ~ ~ ~ ~ ~ ~ ~ ~ Q3 Q3 SBDT, SBCK Timing Relationship WFCK i SBCK SBDT ii Q R S T U V W iii 1 2 3 4 5 6 7 8 i) SBCK is set to `L' for approximately 10us after WFCK becomes negative edge. ii) If SOS1 is `L', subcode P is output but , if SOS1 is `H', SOS1 is output. iii) If more than 7 pulses are input to the SBCK terminal, subcode data P, Q, R, S, T, U, V, W data are output repeatedly. (Notice) Value of $B2 Address xxxx_x11x Value of Others BCK Pin External SHOCK perception signal (ATSC) with it is used Both SBDT and SBCK are Used. 53 S5L9291X DIGITAL SIGNAL PROCESSOR CD TEXT If TextOn is `L' at $95 Command Register, Subcode data are provided through SBCK and SBDT , but if `H', SBCK and SBDT cannot be used. If TextOut is `L' at $95 Command Resister, Q Datum is provided through SBCK,SQDT, but if `L', text data, instead of Qdatum, are output. Text data are output one bit at a time through the SQDT at the Falling Edge of SQCK. First, CRC 4bit datum, in which each Pack(16bit) may have or not have an error, is output, and then the real Text data are output from MSB to LSB. For example, if the first bit of CRC is `H', it means that the first Pack has no error. SQCK,SQDT,S0S1 Timing Relationship S0S1 SQDT SQCK TextOut SQOK Q Data 80 clocks 4bits CRC 4bits 0 16Bytes Pack1 16Bytes Pack2 520 clocks 16Bytes Pack3 16Bytes Pack4 SQOK CRC Data ID1(Pack1) 0 0 0 0 MSB R1 S1 T1 U1 V1 W1 R2 LSB MSB S2 T2 U2 V2 ID2(Pack1) W2 R3 S3 T3 LSB U3 V3 W3 SQDT SQCK TextOut crc1 crc2 crc3 crc4 54 DIGITAL SIGNAL PROCESSOR S5L9291X ECC (ERROR CORRECTION CODE) If the data on the disc is damaged, the ECC (Error Correction Code) block is used to correct data. The CIRC (Cross Interleaved Reed-Solomon Code) is used to correct to 2 errors for C1 (32, 28) and 4 erasures for C2 (28, 24). For error correction, the data is processed in 1 symbol of 8-bit. Furthermore, the ECC block has the pointer function which generates the C1 pointer for C1 correction and C2 pointer for C2 correction. C1 and C2 pointers output flags for ECC processed data to indicate that the data has error. This flag signal is input to the interpolation block and used to process the error data. The error correction results can be monitored through MNT3-MNTO terminals. (Related Command Register: $A9, TALK[2:0]) Mode C10 error C11 error C12 error C1 correction impossible C20 error C21 error C22 error C23 error C24 error C2 correction impossible 1 C2 correction impossible 2 MNT3 ECFL3 0 0 0 1 0 0 0 0 1 1 1 MNT2 ECFL2 0 0 1 0 0 0 1 1 0 0 1 MNT1 ECFL1 0 1 0 0 0 1 0 1 0 1 0 1 1 MNT0 ECFL0 0 0 0 0 1 1 1 1 C1 flag = reset C1 flag = reset C1 flag = set/reset C1 flag = set C2 flag = reset C2 flag = reset C2 flag = reset C2 flag = reset C2 flag = reset C2 flag = set Copy C1 flag Comment INTERPOLATION When a burst error is generated on the disc, there are cases when the data cannot be corrected even with the ECC process. The interpolator block uses the ECC'S C2 pointer to interpolate the data. The audio data is input for L/R-ch in 8-bit C2 point, lower data 8-bit, and upper data 8-bit order, respectively, to the data bus. If C2PO terminal is `H' and there is only one error, the average value is interpolated, but, if there are 3 continuous errors, all values are hold interpolated. If LRCK is `L' for one LRCK cycle, R-ch data is output, and, if `H', L-ch is output. The timing clock in the interpolator block is shown below. A B C D E F G H I J C2 Pointer B: Average value interpolation F = E = D: All value hold interpolation G: Average value interpolation 55 S5L9291X DIGITAL SIGNAL PROCESSOR SERIAL AUDIO DATA INTERFACE Converts the 16-bit parallel data sent by the interpolation block to serial data. S5L9291X supports the following serial audio data format. The LRCK frequency for 1X is 44.1kHz and 2X is 88.3kHz. Fs = 44.1/88.2kHz LRCHO 12 BCKO SADTO R-CH (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L-CH (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24 25 48 1 MUTE & ATTENUATION The mute signal can be accepted in two ways. * * When mute port (pin #: 44) is "H" When $91 command register's D7 bit is "H" The audio data is either muted or reduced based on the mute signal and ATTN signal of the $91 command register. Zero Cross Mute After ZCMT of the $91 command register is set to `H', and the mute signal becomes `H', and the audio data top 6bit all are either `L' or `H', the audio data is muted. Mute When ZCMT of $91 command register is `L' and the mute signal becomes `H', the audio data is muted. Attenuation The signal is reduced by the ATTN of $91 command register and mute signals. ATTN 0 0 1 1 MUTE 0 1 0 1 Degree of Attenuation [Db] 0 - -12 -12 Digital Attenuation By referencing command register $5D, 2 = 64 attenuation levels can be controlled. When the reset signal becomes `L', the attenuation level is initialized to 0Db. Dattn Gain = 20 x log 64 6 56 DIGITAL SIGNAL PROCESSOR S5L9291X Soft Mute When the digital attenuation level is controlled from 0Db to -Db, the soft mute function can be configured. DAC Mute When the $91 command register's DAC_MUTE is "H", only the DAC block is muted. Digital Audio Out This digital audio out block outputs 2-channel and 16-bit data to another digital set in serial format based on the digital audio interface format. The advantage of this interface method is that communication is possible with only one pin, that is, additions such as a separate clock are not required. CD digital audio interface format X Channel 1 Y Channel 2 Z Channel 1 Y Channel 2 X Channel 1 Y Channel 2 SubFrame 1 Frame 191 SubFrame 2 Frame 1 Frame 0 Start of Block 1) 1 block = 192 frame 2) 1 frame = 2 subframe 3) Frame 0, channel 1 - Block sync preamble, Z included Ch.1 format 4) Frame 1, channel 1-frame 191, channel 1 - Ch.1 sync preamble, X included Ch.1 format 5) Frame 0, channel 2-frame 191, channel 2 - Ch.2 sync preamble, Y included Ch.2 format 0 34 78 Preamble AUX LSB Preamble AUX Data Audio Data Valid Data User Data Channel Data Parity Data Audio Data MSB 27 28 29 30 31 VUCP Each subframe is composed of 32 time slots, and audio data is included in the subframe. Two subframes make one frame, which has both left and right stereo signal components; 192 frames make one block, which is in the control bit data unit. 57 S5L9291X DIGITAL SIGNAL PROCESSOR Digital Audio Interface Timing Chart fs = 44.1kHz 128fs bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 ... bit n bit24 bit25 bit26 bit27 bit28 bit29 bit30 bit31 Digital Audio Out Source Coding Channel Coding (Biphase Mark) Preamble Z 58 DIGITAL SIGNAL PROCESSOR S5L9291X SUBFRAME FORMAT Preamble (4 bits): The preamble has each subframe and block sync data. The preamble is not converted to biphase signal to maintain the inherent characteristic of the sync. On the other hand, it starts with the values opposite the phase 1 values of all the. The preamble requires three patterns, that is, a pattern to distinguish between and right and patterns that indicate start of the block. These patterns are shown. Preceding State "X" "Y" "Z" 0 Channel Coding 11100010 11100100 11101000 00011101 00011011 00010111 Subframe 1 Subframe 2 Subframe 1 and block start 1 Preamble `X' is the channel 1 sync; preamble `Y' is the channel 2 sync; and preamble 3 is to show the start sync of the block. The reason that there are 2 sync patterns for preamble is that the value reverses according to the phase of the previous data. AUX (4 bits): Auxiliary data area. Audio data (20 bits): Although the audio data resolution for the CD transmitted to digital out is usually 16 bits, it can also be transmitted as 20 bits or 24 when AUX is to be included. This area is LSB first. Validity bit (1 bit): If the audio sample word can be converted to analog audio signal, the validity bit to `1' and, if not, to `0'. For the CD, set it to `0'. User data (1 bit): This domain is used to transmit the subcode data for CD. Control status data (1 bit): Data is input for each subframe, and 192 subframes must be gathered to make one control data. This domain has both the consumer mode and professional mode, of which S5L9291X the consumer mode. The control status data for CD has the following meaning. Parity data (1 bit): Use even parity 59 S5L9291X DIGITAL SIGNAL PROCESSOR Bit 0 1 2 3 4 5 6-7 8 - 15 16 - 19 20 - 23 24 - 27 28 - 29 Control Status Data 0: Consumer use, 1: Professional use 0: Normal audio, 1: Non audio mode 0: Copy prohibit, 1: Copy permit 0: No pre-emphasis, 1: Pre-emphasis Reserved = 0) 0: 2 channel, 1: 4 Channel 00: Mode 0, reserved 10000000: 2 channel CD player User bit channel = CD subcode V bit optional Source number ( = 0000) Channel number ( = 0000) Sampling frequency: 44.1kHz = 0000 Clock accuracy 00: Normal accuracy 10: High accuracy 01: Variable speed Don't care (all zero) 30 - 191 60 DIGITAL SIGNAL PROCESSOR S5L9291X SIGMA-DELTA STEREO DAC As a digital-to-analog converter that uses the modulation, the DAC installed in S5L9291X is composed of the digital attenuation, de-emphasis filter, FIR filter, SINC filter, digital sigma-delta modulator, analog post-filter, antiImage filter etc. Normal input/output characteristics exist at 20kHz. It has SNR (Signal to Noise Ratio) above 90Db. Timing Chart Fs = 32/44.1/48kHz LRCHI 12 BCKI SADTI R-CH (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L-CH (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24 25 48 1 32/44.1/48kHz Sampling Frequency (Fs) Support (External Master Clock Support) If the DAC master clock is applied to the RFCK terminal (PIN#: 53) in 384 x Fs cycle, it supports 3 sampling frequencies. If the command register $94's MSCKSW is "H" and command register $A9's RFCK_OEN is "L", the external master clock can be applied to the RFCK terminal. X1, X2 Speed Support If the command register $93's DFCK is set to "H", the internal data input rate becomes 2*Fs and the speed becomes 2X. APPLICATION CIRCUIT 46 VDDD_DAC 41 VDDA_DAC 1uF 0.1uF 100K 10uF 0.1uF 10uF 0.1uF 10uF 1uF 0.1uF 100K 10uF Lch Rch 47 VSSD_DAC 44 VAAS_DAC 45 RCHOUT 40 LCHOUT 42 VHALF 43 VREF 61 S5L9291X DIGITAL SIGNAL PROCESSOR 10-Band EQ. Filter It has a Digital Filter inside the chip for equalizing the signal. It is possible to control EQ Gain using Command Resister $A0 - $A2,A5 and three band EQ Digital Filter features are as follows. Audio input pre-scaler 0 - 200hz g1 Limiter Audio output 200hz - 8kHz g2 8Khz - 18kHz g3 g1 : Bass gain, g2 : Mid gain, g3 : high gain 3Band EQ. Block Diagram 3Band EQ. Frequency Response 62 DIGITAL SIGNAL PROCESSOR S5L9291X 3Band EQ. Bass Frequency Response 3Band EQ. Mid. Band Frequency Response 63 S5L9291X DIGITAL SIGNAL PROCESSOR 3Band EQ. High Band Frequency Response Micom Command flow To drive the 3Band EQ., first the gains of each band must be set and the values must be converted to 16 (hex). Examples of this is as follows: Pre Scale : 0Db, Bass : 10Db, Mid : -3Db, High : -3Db Pre Scale gain = 10(0/20) = 1 (dec) = 001.00000 (bin) = 20 (hex) Bass gain = 10 Mid gain = 10 (10/20) = 3.162277 (dec) = 011.00101 (bin) = 65 (hex) (-3/20) = 0.707945 (dec) = 000.10110 (bin) = 16 (hex) High gain = 10(-3/20) = 0.707945 (dec) = 000.10110 (bin) = 16 (hex) After calculating the pre-scale gain and different gains of each band, micom command is input in the order as shown in the flow chart below. 64 DIGITAL SIGNAL PROCESSOR S5L9291X EQ.Start EQ.End Pre Scale Gain $A520 Soft Mute On $5dfe Bass Gain $A065 Wait 23.2ms Mid Gain $A116 3 Band EQ. Off $A400 High Gain $A216 Soft Mute Off $5d00 Soft Mute On $5Adfe Wait 23.2ms 3 Band EQ. On $A440 Soft Mute Off $5d00 Normal (Default) Pre-Scale BASS MID HIGH $A520 $A020 $A120 $A220 +3Db $A52D $A02D $A12D $A22D +6Db $A53F $A03F $A13F $A23F +10Db $A565 $A065 $A165 $A265 -3Db $A516 $A016 $A116 $A216 -6Db $A510 $A010 $A110 $A210 -10Db $A50A $A00A $A10A $A20A 65 S5L9291X DIGITAL SIGNAL PROCESSOR DIGITAL CLV SERVO This block controls the spindle motor speed by using RFCK and WFCK data to generate the control. Digital CLV Servo control related Command Registers are $93, $94, and $98 - $9E. Forward (Kick) Mode Mode ($99) that rotates the spindle motor in forward direction. SMDP H SMDS Hi-Z SMEF L SMON H Reverse (Brake) Mode Mode ($99) that rotates the spindle motor in the reverse direction. SMDP L SMDS Hi-Z SMEF L SMON H Stop Mode Mode ($99) that stops the spindle motor. SMDP L SMDS Hi-Z SMEF L SMON L Speed (CLV-S) Mode ($99) Controls the spindle motor during a track jump or if the EFM phase is unlocked. Although the pulse width of the frame sync signal detected from the EFM signal is exactly 22T in PLCK cycle (T), it can be greater or less than 22T depending on the player status. WB and WP of the command register $98 are used to control the frame sync detection cycle. SMDP L : deceleration H : acceleration Hi-Z : remain SMDS Hi-Z SMEF L SMON H Detected Frame Sync Pulse Width 21T = 22T 23T SMDP L (deceleration) Hi-Z (remain) H (acceleration) Comment If the command Register $98's GAIN is `L', the SMDP output is output after it has been attenuated by -12Db, but if `H', it is output without being attenuated. 66 DIGITAL SIGNAL PROCESSOR S5L9291X P22T N22T SMDP deceleration under 22 t acceleration over 22 t = 22 t Phase Error Signal RFCK/4 WFCK/4 DOWN UP SMDP tHW = 288T WFCK tHW = 288T SMDS tHW = 294T (THW-279T)*32 = 480T < SMDS output waveform in Phase (CLV-P) Mode: SGAIN = 32, rise_mtval = 279 > 67 S5L9291X DIGITAL SIGNAL PROCESSOR XPHSP (CLV-A) Mode (Command Register : $99) In this normal operation mode, the speed mode and phase mode are change alternately by the lock signal. After the LKFS signal generated by the frame sync block is sampled in WFCK/16 cycles and is detected to be `H', the phase mode executes and, if it is detected as `L' eight consecutive times, the speed mode automatically executes. High Speed (CLV-H) Mode (Command Register : $99) In Jump mode, in which servo has to traverse about 20,00 track roughly, servo moves from inner track of disc to outer. In that case, mirror signals about 20KHz are overlapped in EFM. So servo is to be unstable in Speed-mode, because false Mirror peak level , which is larger than Frame Sync, is detected. In high Speed Mode, Peak Hold uses 8.4672MHz/256 cycle and Bottom hold uses RFCK/16 or RFCK/32 cycle, so it make possible to eliminate the Mirror signals and for servo to be stable LOCK generation If the LKFS signal remains at `L' for the frame time, provided by Micom Command $99's UNLOCK[1:0], or for less, LOCK remains at `H'. However, if it remains at `L' for more than the given frame, the LOCK changes to `L'. The time in LOCK is the same for 1X and 2X speed. Additional Functions ($9B's POS must be set to = `H') 1) SMDS masking This function prevents sensitive CLV servo response to small frequency error changes. If the SME of $9A is set to `H', it operates in the SMDS masking mode (dead zone enable). The SML[1:0] masking range of $9B is set, and, if $9A's SMM bit is `H', SML value becomes the absolute value of the masking range, set by 9D'h SMOFFSET[3:0], but if `L', then the value is set to the one shown in the table below. If SMDS frequency error, that is, WFCK high width is within the masking range, the SMDS output is PWM of 50:50 or Hi-Z is output. (Determined by $9A's STRIO) If SMDS masking occurs, SMDP output is masked automatically and Hi-Z is output. Command order : $9B(SML) $9D(SMOFFSET) $9A (SME, SMM) SML[1:0] 00 01 10 11 masking error range (SML = `L') 0 % 6.25 % 12.5 % 25 % < SML[1:0] setting > 68 DIGITAL SIGNAL PROCESSOR S5L9291X SMDS High width (t) 288t WFCK WFCK High width (t) 1t = 1/8.4672MHz 288t masking error area (deas zone area) Maximum error area < Dead Zone Area > 69 S5L9291X DIGITAL SIGNAL PROCESSOR SMDP masking When the SMDS masking is enabled, the SMDP output is automatically masked in the dead zone area. There are two modes for masking only the SMDP without masking the SMDS. In the first mode, if $9A's SME is set to `L' and PME is set to `H', the SMDP masking mode operates. At this time, if the phase error is greater than 50% or 25% of the WFCK frequency error (determined by $9B's PML), SMDP output is masked. That is, the output is Hi-Z. This is to reduce the phase error effect at the state in which the frequency error is not sufficiently small. In the second mode, after setting SME and PME of $9A, PCEN of $99 can be used to set SMDP masking. In this case, if PCEN of $99 is set to `H' and WFCK frequency error enters the dead zone area set by SML, the SMDP output is maked to Hi-Z. Command order : $9B(PML) $9A(PME), $9B(SML) $99(PCEN) CLV emergency mode (ECLV) When there are events such as a focus drop, an unstable EFM is input and this in turn causes the spindle motor to overload. To prevent such an overload, the Micom notifies the CLV servo of such emergency conditions, and then CLV servo outputs H, Hi-Z and L repeatedly in regular intervals. This is all executed by the micom, which sets the ECLV of $93 to `H' and changes the CLV mode to CLV-S mode. Then, SMDS outputs Hi-Z and SMDP outputs H, Hi-Z and L repeatedly in an interval determined by ECLV_PD of $93. ECLV_PD 1 0 Comment bottom hold pulse interval peak hold pulse interval Command order : $93(ECLV, ECLV_PD) $99(CM3,CM2,CM1,CM0) Defect response mode If the EFM enters as `L' for a specific time due to a Scratch or defect, there is no PLL control, which fixes the PLCK to any frequency; this in turn fixes the WFCK and consequently the CLV servo output is fixed in the direction of acceleration or deceleration. In such a case, the final CLV speed can be reduced when normal EFM re-enters. If CLV_DFCT of $A2 is set to `H', the CLV servo outputs, SMDP and SMDS, can be output as Hi-Z and 50:50, when EFM width is greater than 64t to prevent deceleration or acceleration. Over sampling output The SMDS output frequency is 7.35kHz at 1X speed and 14.7kHz at 2X speed. These are within the audio frequency range, so they be used as normal audio output noise source. Therefore, OVSPL of $98 can be set to `H' and SMDS and SMDP frequencies can be over sampled by four times at 7.35KHz * 4 = 29.4kHz and output. If OVSPLMD of $98 is set to `H', the SMDS becomes tri-state t output and, if set to `L', SMDS become a PWM output. CLV IDLE mode This mode rotates the spindle motor at a fixed rate regardless of the EFM input. To operate in the CLV IDLE mode, the $9E's SOFFSET[7:0] value, which represents the SMDS high width, must be set. Furthermore, if $99's CLV_IDLE is set to `H', the SMDP output becomes Hi-Z, and SMDS outputs High for the duration of SOFFSET set value * 118ns in one cycle and outputs Hi-Z in the remaining intervals. 70 DIGITAL SIGNAL PROCESSOR S5L9291X SMDS SOFFSET Hi-Z < SMDS output > SMDS gain control If the pickup or spindle motor is changed, the entire CLV loop transfer function changes and thus CLV gain must be controlled. The CLV servo is changed to PI controller type; we can assume that the frequency error output SMDS controls the P gain and the phase error output SMDP controls the I gain. SMDS gain can be set to 9B'h SGAIN[2:0] , where gain values of SGAIN are shown below. In terms of a graph, the gain is the slope. SGAIN[2:0] 000 001 010 011 100 101 110 111 Gain Value 1 2 4 8 16 32 64 128 < SMDS gain setting > rise_mtval 0 144 216 252 270 279 283 285 SMDS High width (t) 288t WFCK High width (t) 1t = 1/8.4672MHz 288t rise_mtval Maximum error area < SMDS gain vs SMDS output > 71 S5L9291X DIGITAL SIGNAL PROCESSOR There is an additional feature which allows the addition of an offset to WFCK frequency error for output. If $9D's SPLUS is set to `H' and $9E's SOFFSET[7:0] is set, the SOFFSET value is added to the frequency error, and the product of this value and the gain is output to SMDS. SMDP gain control The 9B'h POS must be set to `H' for SMDP gain control. Furthermore, SMDP gain must be set to $9A's PGAIN[1:0]. The clock resolution, which measures WFCK and RFCK's phase error, must be set to $9A's PKSEL. PGAIN[1:0] 00 01 10 11 < Phase error resolution clock setting > If POFFSET[7] is `H', the value is subtracted and, if `L', added. . SMDS output Mode If $9A's STRIO is set to `H', the SMDS is output in tri-state (H, Hi-Z, L) states in phase mode. If $9D's SDD is set to `H', the SMDS outputs as Hi-Z in phase mode if the WFCK frequency error is a deceleration error. Even if SMDS is output as Hi-Z, this mode can reduce the power consumption by utilizing the principle of deceleration due to motor friction. 72 DIGITAL SIGNAL PROCESSOR S5L9291X DIGITAL PLL The existing Digital PLL (DPLL) is used to enter the wide capture range PLL mode, which allows the frequency of the frequency synthesizer, which supplies the DPLL clock, to follow the bit rate change of the EFM signal. Once in the wide capture range PLL mode, the jitter-free mode can be set to suppress the SRAM jitter that may be generated by the change in the input/output rate of the internal SRAM buffer. Furthermore, multi-speed CLV mode in 16 levels from 1X to 2X is possible. PLL1 XIN PHASE DETECTOR1 1/P1 XINM DPDO1 LOOP FILTER1 M1 WIDE 1/M1 VCO1ON CNTVOL1 VCO1O VCO1 1/S1 M1 REF<1:0> EFMI WFCK PLCK DPLL PLCK8M PLL2 MAXT COUNT MAXT<8:0> DIVM DETERMINE to EFM demodulation MUX PLL2REF JITFREE P2 PHASE DETECTOR2 XIN 1/P2 DPDO2 LOOP FILTER2 1/M2 M2 XOUT VCO2 XOUT16M CNTVOL2 1/S2 S2 to ECC & Interpolation or CLV < Block Diagram > 73 S5L9291X DIGITAL SIGNAL PROCESSOR PLL1, a frequency synthesizer which supplies DPLL reference clock, uses the input (16.9344MHz) from the crystal to generate a clock of frequency that is a multiple of PLCK frequency. PLL2 is a frequency synthesizer which supports the entire speed range CLV or jitter-free mode. Therefore, PLL2 is set to the power down mode when it is not used in normal 1X and 2X mode or jitter free1 mode. In the entire speed range CLV mode, the output frequency of PLL2 the crystal input to be used as either the CLV mode reference clock and data operation(ECC, interpolation) reference clock; in the jitter free2 mode, the output together with the DPLL plck8M input is used as data operation reference clock. The entire speed range CLV mode and jitterfree2 mode cannot be set simultaneously. The equation of the output frequency from the frequency synthesizer is as follows. Divider value changes with mode. Fout = Fin x m pxs Fin: input frequency, Fout: output frequency p: pre-divider(=DIVP+2), m: main-divider(DIVM+8), s: post-scalor(2DIVS) In the entire speed range CLV mode, once the values for DIVS1 and DIVP1 of 8A address are set according to speed, the remaining divider values are automatically set. Commands according to speed are as follows. Command speed 0.5 ... 1 1.04 1.09 1.14 1.2 1.26 1.33 1.41 1.5 1.55 1.6 1.66 1.71 1.78 1.85 1.92 2 ... 8A 6E ... 56 55 54 53 52 51 50 4F 1E 1D 1C 1B 1A 19 18 17 16 ... F4 00 F0 00 74 DIGITAL SIGNAL PROCESSOR S5L9291X ELECTRICAL SHOCK PROOF (ESP) The ESP(Electrical Shock Proof) Block has the data compression/restoration functions, recovery decompression/restoration functions for anti-shock proofing of compact disc players and DRAM memory control function. The compression ratio is about 4/16bit, 5/16, and 6/16 and shock proof data storage memory sizes are 4M/4Mx2/16M DRAM. FEATURE 1) 2-Channel Processing 2) Serial Data Input : 2's complement, 16-bit/MSB first 3) Anti-Shock Memory Controller 4) ARS(Anti-Rolling System) support : X1 X4 Compression possible 5) Compression Method n n n n n n n n n 4-Bit Compression Mode 2.91s/Mbit 5-Bit Compression Mode 2.34s/Mbit 6-Bit Compression Mode 1.95s/Mbit Full-Bit Non-Compression Mode 0.743s/Mbit 4M DRAM (1Mx4 bits) 8M DRAM (1MX4 bits 2EA) 16M DRAM (4MX4 bits) Serial Command Write and Internal State Read-Out Data Residual Quantity Detector : 16-Bit Output 6) 3 Internal DRAM Configurations Selectable 7) Microcontroller Interface No Compression (88.2KHz) LRCKi BCKi SADTi SPC Encoder Data[3:0] Addr[11:0] RAS External DRAM 1. 4M 2. 4Mx2 3. 16M (44.1KHz) LRCKo BCKo SADTo DRAM I/F PSC Decoder CAS WE OE GND No Compression < ESP Block Diagram > 75 S5L9291X DIGITAL SIGNAL PROCESSOR Anti-Shock Operation The shock-proof mode uses the data storage dram. If the Micom Command $B0's MSON = `H', shock-proof operation executes. Encode Sequence In the encode sequence, the audio data from the CD data processor (CDP) is encoded through the ESP encoder and the compressed data is stored in the data storage DRAM. Encode Sequence Internal Stop If there is an data storage DRAM buffer overflow or shock(JITB=='L' or CMD_SHOCK=='H'), ESP is stopped internally regardless of the Micom Command $B0's MSWREN. The encoding starts when there is a match by Compare-Connect Sequence or a Direct-Connect Command input. Decode Sequence The ESP Decoder checks the system stability in the micom and the presence of the data which can be sent to the DRAM. If they both check out to be normal, the micom command $B0's MSRDEN is set to `H' and decoding starts. Before the decoder starts, the mute/attenuation function for data output control is put on normal. Data Compare-Connect Sequence Encoding stops when it detects a CDP system shock or DRAM overflow. Once the system shock stabilizes or the DRAM data is less than the amount specified in the MICOM PGM and the micom command $B0's MSDCN1(or = MSDCN2) = MSWREN = `H', it executes the Data CompareConnect Start Command. If the data compare-connect matches normally or direct - connect command is input, the data compare connect processing comes to an end and encoding begins. The audio data input at this time is directly connected to the last valid data. DRAM Refresh Method The 16 cycle's RAS Only refresh begins at the MSON Rising Edge. DRAM Address 1) To address the basically supported 4M/8M(4M+4M)/16M DRAM, the address register size is 22 bit and the DRAM is accessed in the form of a circular buffer. 2) RA : The data address read from the DRAM for decoding is stored. As long as it is not "empty", the read operation continues. "Empty" state occurs when RA and VWA becomes the same. 3) WA : The DRAM address to which the encoded data is stored. If compare-connect is operating or "Ovfl (Overflow)" condition exists, this also stops along with the encoding. When Compare-Connect Sequence begins, the data written after VWA becomes meaningless and writing must begin again starting from the address directed by VWA. 4) VWA : updated to the current WA value by the micom's WAQV. 5) As shown in the following figure < WA / RA Mapping> , RA becomes the address of the first data to be decoded and WA becomes the address value following the last encoded data. Therefore, as WA increases and the writing ends and it becomes the same value as RA, DRAM overflows and the encoding stops. 76 DIGITAL SIGNAL PROCESSOR S5L9291X VWA RA x1 WA Encoded Data x2 VWA WA x1 x2 RA Power On Sequence ESP Initial Sequence ESP Reset Sequence ESP Initial Sequence Memory & Compression Mode & 12/16-Bit Compare Selection Setting $B1,xxxx_x0xx 1-Bit DAC MUTE On $91,0000_1000 ESP Reset Sequence ESP On/Reset $B0,0101_0001 Key Operation Sequence Soft ATTN Off $5D,0000_0000 77 S5L9291X DIGITAL SIGNAL PROCESSOR $B1 Address initial setting DRAM Selection 4M DRAM 8M DRAM 16M DRAM FLAG6 Setting Selection JITB in Falling Edge of RFCK JITB in Rising Edge of RFCL JITB L JITB H 12/16-Bit Compare Selection 12-bit Compare 16-bit Compare Compression Mode Selection 4-bit Mode 5-bit Mode 6-bit Mode Full-bit Mode $B1,xxxx_xx00 $B1,xxxx_xx01 $B1,xxxx_xx10 $B1,xxxx_xx11 $B1,xxxx_1xxx $B1,xxxx_0xxx $B1,xx00_xxxx $B1,xx01_xxxx $B1,xx10_xxxx $B1,xx11_xxxx $B1,00xx_xxxx $B1,01xx_xxxx $B1,1xxx_xxxx 78 DIGITAL SIGNAL PROCESSOR S5L9291X KEY OPERATION SEQUENCE Key Operation Key Operation Sequence ESP On/Off Toggle Key? No ESP On ? Yes Play Key? Yes ESP Start Sequence Yes No No Soft ATTN On (FadeOut) Sequence Special Key? No Yes (Skip/Stop/ Pause/Search Key) End Waiting Fade Out Completed(23.2ms) Soft ATTN On (FadeOut) Sequence No Through Mode Sequence ESP On ? Waiting Fade Out Completed(23.2ms) ESP Reset Sequence Yes Yes ESP Reset Sequence Skip Key? No Yes Stop Key? Stop No Go Next Music Pause Key? No Yes ESP Start Sequence Pause Key Sequence Search Key Sequence Through Mode sequence means a Normal 1x play. In Pause Key Sequence , Play/Skip/Stop key must be entered one more time. 79 S5L9291X DIGITAL SIGNAL PROCESSOR Pause Key Sequence Pause Key Sequence Waiting Key Input Play Key? Yes No Skip Key? No Stop Key? No Yes Yes ESP Start Sequence Go Next Music Stop 80 DIGITAL SIGNAL PROCESSOR S5L9291X Search Key Sequence Search Key Sequence 1-Bit DAC MUTE Off $91,0000_0000 X1 Fast Search ??????? Search Key Off? Yes No ESP Start Sequence 81 S5L9291X DIGITAL SIGNAL PROCESSOR ESP Start Sequence ESP Start Sequence Encode Command $B0,10000001 S0S1 Falling Edge & SQOK Yes 1-Bit DAC MUTE Off $91,0000_0000 No ESP Encode/Decode Sequence 82 DIGITAL SIGNAL PROCESSOR S5L9291X ESP Encode/Decode Sequence ESP Encode/Decode Sequence S0S1 Falling Edge Yes ESP Status Read ($B5,$B6) No FLAG6? 0 ENCOD/ SHOCK? 1 MSEMP? No SubQ Read CRC Check Yes SQOK? Yes WAQV Command $B0,10100011 Track Back Jump & Compare Routine No 4-Block CRC-Bad? No Yes FOK Error 100ms 0 CMD_Shock Enable $B2,0000_0101 $B2,0000_0100 Wait minimum 0.9ms Memory Residual Read ($B6) Compare Command $B0,1010_1101 ESP Status Read ($B5) Yes MSEMP? No Soft ATTN On Sequence DCOMP? 1 No Passes the position to be connected? 0 ESP Reset Sequence Yes 83 S5L9291X DIGITAL SIGNAL PROCESSOR Soft ATTN On Sequence In Soft Attn Command, Fade_in or Fade_out functions can be operated within 23.2ms Fade Out :when $5D,1111_1110 Command is entered, Sound is fade out within 23.2ms Fade In: When $5D,1111_1110 Command is entered, that is , from the start position of the music in Fade Out, when $5D 0000_0010 Command is entered, sound is fade in within 23.2ms. Soft ATTN On Sequence Soft ATTN On Sequence Soft ATTN On $5D,0000_0010 Fade Out ? Yes Soft ATTN On $5D,1111_1110 Fade Out within 23.3ms No Fade In No Yes No Fade Out State? Yes Forbidden Soft ATTN On $5D,0000_0010 Fade In within 23.2ms Attenuation Level Setting $5D,xxxx_xx10 84 DIGITAL SIGNAL PROCESSOR S5L9291X ESP Time Display Sequence ESP Time Display Sequence S0S1 Falling Edge Yes Q=SubQ Read No Q and Qdisplay same music Yes Memory Residual Read ($B6) Qstored=Valid Data Size No Qlast=last Q of last music1 if( time of music2< DRAM Size) Qlast2=last Q of last music2 Wait the Increment Timer count up Qdisplay=Q-Qstored Qdisplay=Qdisplay+1 Qdisplay > Qlast Yes No 85 S5L9291X DIGITAL SIGNAL PROCESSOR ESP Time Display Figure CD Reading Position Qlast Q Qstored Hearing(Displaying) Position Qdisplay time music1 music2 ESP DATX Sequence In Normal X1 speed mode, ESP ON, or external MP3 mode, for obtaining the DATX Output. $91,0000_0001 Command is used. 86 DIGITAL SIGNAL PROCESSOR S5L9291X PACKAGE DIMENSION 16.00 0.20 14.00 0-7 0.127 + 0.073 - 0.037 16.00 0.20 14.00 100-TQFP-1414 0.08 MAX #100 #1 0.50 + 0.07 0.20 - 0.03 0.05-0.15 (1.00) 1.00 0.05 1.20 MAX NOTE: Dimensions are in millimeters. 0.45-0.75 87 S5L9291X DIGITAL SIGNAL PROCESSOR NOTES 88 |
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